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Bit
2
Name
CNTDIR
Reset
0
Access
RW
Description
Non-Quadrature Mode Counter Direction Control
The direction of the counter must be set in the OVSSINGLE and EXTCLKSINGLE modes. This bit is ignored in EXTCLKQUAD mode
as the direction is automatically detected.
Value
0
1
Mode
UP
DOWN
Description
Up counter mode
Down counter mode
1:0
MODE
0x0
RW
Mode Select
Selects the mode of operation. The corresponding clock source must be selected from the CMU.
Value
0
1
2
3
Mode
DISABLE
OVSSINGLE
EXTCLKSINGLE
EXTCLKQUAD
Description
The module is disabled
Single input LFACLK oversampling mode (available in EM0-EM2)
Externally clocked single input counter mode (available in EM0-EM3)
Externally clocked quadrature decoder mode (available in EM0-EM3)
22.5.2 PCNTn_CMD - Command Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Offset
0x004
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1
LTOPBIM
0
W1
Load TOPB Immediately
This bit has no effect since TOPB is not buffered and it is loaded directly into TOP. For EFM32G revisions A and B: Load PCNTn_TOPB
into PCNTn_TOP. Please see the device datasheet for a description on how to extract the chip revision.
0
LCNTIM
0
W1
Load CNT Immediately
Load PCNTn_TOP into PCNTn_CNT on the next counter clock cycle.
22.5.3 PCNTn_STATUS - Status Register
Offset
0x008
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2011-04-12 - d0001_Rev1.10
316
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